Field of the Invention
The present invention relates to a data processing apparatus and method for decoding program instructions in order to generate control signals for processing circuitry of the data processing apparatus.
Description of the Prior Art
Data processing circuitry will typically have access to a set of registers that are arranged to store operands for access by that data processing circuitry whilst it is performing data processing operations. The data processing operations that the data processing circuitry performs are typically defined by a series of instructions, where each instruction includes a register specifier field identifying the registers that are to form source and/or destination operands for the associated data processing operation.
However, the instructions of a particular instruction set are typically constrained to a certain number of bits, and hence it is important to use the bit encoding space of the instruction as efficiently as possible in order to enable the required information to be encoded within the instruction. With regard to the register specifier field, it is hence desirable wherever possible to reduce the number of bits required to specify the registers to be used as source and/or destination operands. By doing so, this will free up more space within the instruction to encode other information, and/or allow more registers to be specified within a particular number of bits.
One known approach for reducing the number of bits needed to encode the registers within the register specifier field of the instruction is often referred to as register renaming. In accordance with register renaming, there are a relatively small number of register identifiers that can be specified within the instruction. However, the processor itself has access to more physical registers than can be named directly in the instruction, and register rename hardware within the processor is used to rename registers in certain situations in order to achieve a higher degree of parallelism within the processor, and hence increase performance. However, such an approach is typically only used in high performance processors having multiple parallel execution paths, where the hardware overhead involved in performing register renaming is considered worthwhile for the performance benefits achieved. In addition, register renaming limits the ability of the compiler to take advantage of the actual physical registers available. Indeed, often the compiler must store operand values to memory because there are not enough architecturally visible registers for it to use within the program instructions.
Another known technique for reducing the number of bits required in the instruction space to identify registers is referred to as register windowing. In accordance with a typical register windowing technique, several sets of registers are provided for different programs, or different parts of a program. The instructions themselves specify registers within a predetermined range, but the processor recognises the movement from one part of the program to another, or from one program to another, for example through the monitoring of procedure calls. The state of the hardware is then updated as appropriate so as to cause the register specified by an instruction to be mapped to the actual window of registers applicable for the current context. However, such an approach lacks flexibility when seeking to perform operations on values from multiple contexts due to the different register windows associated with each context, and typically requires special instructions to change the context and accordingly change the mapping between the registers specified in the instruction and the actual physical registers accessed.
Accordingly, it would be desirable to provide an improved mechanism for efficiently encoding registers within instructions.